As is well-known, a cache stores information for a computer or computing system in order to decrease data retrieval times for a processor. Some examples of computing systems are a personal digital assistant, internet tablet, and a cellular phone. The cache stores specific subsets of information in high-speed memory. A few examples of information are instructions, addresses, and data. When a processor requests a piece of information, the system checks the cache first to see if the information is stored within the cache. If so, the processor can retrieve the information much faster than if the data was stored in other computer readable media, such as, random access memory, a hard drive, compact disc read-only memory (CD ROM), or a floppy disk.
Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions. The fabrication of an IC incorporating such Very Large Scale Integration (VLSI) must be error free, as any manufacturing defect may prevent the IC from performing all of the functions that an IC or SoC is designed to perform. Such demands require verification of the design of the IC or SoC and also various types of electrical testing after the IC or SoC is manufactured.
As cache sizes increase, so does the impact to yield. Consequently, testing and manufacturing become more complex. Typically, one reduces the impact to yield by allowing a processor to have a predetermined number of defective lines. However, one would need to disable the defective lines during a manufacturing or normal execution. Regardless of the method of disabling the defective lines, one needs to track the defective lines. For example, one needs to track the defective lines across processor reset since the reset may have destroying the tags associated with the defective lines. One solution is placing a fixed number of defective cache lines in dedicated on-core resources. Consequently, this increases hardware requirements. Furthermore, this limits the number of disabled lines by the amount of dedicated resources and may only allow for a fixed number of disabled lines.